The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device that can realize a reduction in GIDL (gate-induced drain leakage) and a method for manufacturing the same.
As high integration of a semiconductor device proceeds, it is becoming more and more difficult to achieve a desired threshold voltage using conventional planar channel structures. Thus, limitations arise and alternate solutions must be present that can overcome these problems brought about by the high integration. Under these circumstances, research has actively been conducted in order to develop semiconductor devices which have three-dimensional channel structures capable of securing an effective channel length while maintaining a high integration. As a result of this research and development, semiconductor devices having recess channels or protrusion channels have already been disclosed in the art. Further, semiconductor devices having saddle fin-shaped channels, in which the recess channel and the protrusion channel are combined, have also been disclosed in the art.
In semiconductor devices having saddle fin-shaped channels, when compared to those semiconductor devices that have the more conventional planar channel structure, an effective channel length can be achieved. Since an effective channel width is increased in fin-shaped channels, then current drivability can also be improved.
The semiconductor device having the saddle fin-shaped channel is structured such that a gate forming area in an active region is recessed to a first depth and portions of an isolation layer which extend from the gate forming area are recessed underneath the gate to a second depth greater than the first depth to expose the front and rear surfaces of the gate forming area recessed to the first depth.
Unfortunately, semiconductor devices having the saddle fin-shaped channel can suffer a threshold voltage problem. Since a gate is structured to cover a channel area, then the threshold voltage (Vt) drop occurs as compared to a semiconductor device which has a recess channel capable of securing reliability in terms of characteristics thereof. In order to cope with this problem, the concentration of boron in the channel is often increased. However, if this is the case, then electric fields in junction areas are intensified, and the junction leakage increases. As a result the refresh characteristics are likely to degrade.
In addition, more conventional semiconductor devices that have the saddle fin-shaped channel configuration are made by using radical gate oxidation fabrication schemes in which the growth of an oxide layer is uniformly implemented irrespective of the directions of silicon lattices for the purpose of reducing off-leakage toward a channel area. In this case, GIDL current increases at the overlapping areas between junction areas and gates. Meanwhile, in the case where the existing dry oxidation scheme is employed instead of the radical gate oxidation scheme, degradations in terms of sub-threshold slope and DIBL (drain-induced barrier lowering) arise, whereby off-leakage increases and refresh characteristics are also likely to deteriorate.
As a result, in the conventional semiconductor device having the saddle fin-shaped channel, a retention time is shortened when compared to the semiconductor device having a recess channel.